
`timescale 1 ns / 1 ps

    module MiniMAC_1Ge_AXI_v1_0_M00_AXIS #
    (
        // Users to add parameters here

        // User parameters ends
        // Do not modify the parameters beyond this line

        // Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
        parameter integer C_M_AXIS_TDATA_WIDTH  = 32,
        // Start count is the numeber of clock cycles the master will wait before initiating/issuing any transaction.
        parameter integer C_M_START_COUNT   = 32
    )
    (
        // Users to add ports here
        
        input wire         int_rst  ,
        input wire         int_clk  ,
        input wire         par_en   ,
        input wire [31: 0] int_data ,
        input wire         int_valid,
        input wire         int_sop  ,
        input wire         int_eop  ,
        input wire [ 1: 0] int_mod  ,

        // User ports ends
        // Do not modify the ports beyond this line

        // Global ports
        input wire  M_AXIS_ACLK,
        // 
        input wire  M_AXIS_ARESETN,
        // Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted. 
        output wire  M_AXIS_TVALID,
        // TDATA is the primary payload that is used to provide the data that is passing across the interface from the master.
        output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] M_AXIS_TDATA,
        // TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte.
        output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] M_AXIS_TKEEP,
        // TLAST indicates the boundary of a packet.
        output wire  M_AXIS_TLAST,
        // TREADY indicates that the slave can accept a transfer in the current cycle.
        input wire  M_AXIS_TREADY
    );
//  //Total number of output data.
//  // Total number of output data                                                 
//  localparam NUMBER_OF_OUTPUT_WORDS = 8;                                               
                                                                                         
//  // function called clogb2 that returns an integer which has the                      
//  // value of the ceiling of the log base 2.                                           
//  function integer clogb2 (input integer bit_depth);                                   
//    begin                                                                              
//      for(clogb2=0; bit_depth>0; clogb2=clogb2+1)                                      
//        bit_depth = bit_depth >> 1;                                                    
//    end                                                                                
//  endfunction                                                                          
                                                                                         
//  // WAIT_COUNT_BITS is the width of the wait counter.                                 
//  localparam integer WAIT_COUNT_BITS = clogb2(C_M_START_COUNT-1);                      
                                                                                         
//  // bit_num gives the minimum number of bits needed to address 'depth' size of FIFO.  
//  localparam bit_num  = clogb2(NUMBER_OF_OUTPUT_WORDS);                                
                                                                                         
//  // Define the states of state machine                                                
//  // The control state machine oversees the writing of input streaming data to the FIFO,
//  // and outputs the streaming data from the FIFO                                      
//  parameter [1:0] IDLE = 2'b00,        // This is the initial/idle state               
                                                                                         
//                  INIT_COUNTER  = 2'b01, // This state initializes the counter, ones   
//                                  // the counter reaches C_M_START_COUNT count,        
//                                  // the state machine changes state to INIT_WRITE     
//                  SEND_STREAM   = 2'b10; // In this state the                          
//                                       // stream data is output through M_AXIS_TDATA   
//  // State variable                                                                    
//  reg [1:0] mst_exec_state;                                                            
//  // Example design FIFO read pointer                                                  
//  reg [bit_num-1:0] read_pointer;                                                      

//  // AXI Stream internal signals
//  //wait counter. The master waits for the user defined number of clock cycles before initiating a transfer.
//  reg [WAIT_COUNT_BITS-1 : 0]     count;
//  //streaming data valid
//  wire    axis_tvalid;
//  //streaming data valid delayed by one clock cycle
//  reg     axis_tvalid_delay;
//  //Last of the streaming data 
//  wire    axis_tlast;
//  //Last of the streaming data delayed by one clock cycle
//  reg     axis_tlast_delay;
//  //FIFO implementation signals
//  reg [C_M_AXIS_TDATA_WIDTH-1 : 0]    stream_data_out;
//  wire    tx_en;
//  //The master has issued all the streaming data stored in FIFO
//  reg     tx_done;


//  // I/O Connections assignments

//  assign M_AXIS_TVALID    = axis_tvalid_delay;
//  assign M_AXIS_TDATA = stream_data_out;
//  assign M_AXIS_TLAST = axis_tlast_delay;
//  assign M_AXIS_TKEEP = {(C_M_AXIS_TDATA_WIDTH/8){1'b1}};


//  // Control state machine implementation                             
//  always @(posedge M_AXIS_ACLK)                                             
//  begin                                                                     
//    if (!M_AXIS_ARESETN)                                                    
//    // Synchronous reset (active low)                                       
//      begin                                                                 
//        mst_exec_state <= IDLE;                                             
//        count    <= 0;                                                      
//      end                                                                   
//    else                                                                    
//      case (mst_exec_state)                                                 
//        IDLE:                                                               
//          // The slave starts accepting tdata when                          
//          // there tvalid is asserted to mark the                           
//          // presence of valid streaming data                               
//          //if ( count == 0 )                                                 
//          //  begin                                                           
//              mst_exec_state  <= INIT_COUNTER;                              
//          //  end                                                             
//          //else                                                              
//          //  begin                                                           
//          //    mst_exec_state  <= IDLE;                                      
//          //  end                                                             
                                                                              
//        INIT_COUNTER:                                                       
//          // The slave starts accepting tdata when                          
//          // there tvalid is asserted to mark the                           
//          // presence of valid streaming data                               
//          if ( count == C_M_START_COUNT - 1 )                               
//            begin                                                           
//              mst_exec_state  <= SEND_STREAM;                               
//            end                                                             
//          else                                                              
//            begin                                                           
//              count <= count + 1;                                           
//              mst_exec_state  <= INIT_COUNTER;                              
//            end                                                             
                                                                              
//        SEND_STREAM:                                                        
//          // The example design streaming master functionality starts       
//          // when the master drives output tdata from the FIFO and the slave
//          // has finished storing the S_AXIS_TDATA                          
//          if (tx_done)                                                      
//            begin                                                           
//              mst_exec_state <= IDLE;                                       
//            end                                                             
//          else                                                              
//            begin                                                           
//              mst_exec_state <= SEND_STREAM;                                
//            end                                                             
//      endcase                                                               
//  end                                                                       


//  //tvalid generation
//  //axis_tvalid is asserted when the control state machine's state is SEND_STREAM and
//  //number of output streaming data is less than the NUMBER_OF_OUTPUT_WORDS.
//  assign axis_tvalid = ((mst_exec_state == SEND_STREAM) && (read_pointer < NUMBER_OF_OUTPUT_WORDS));
                                                                                                   
//  // AXI tlast generation                                                                        
//  // axis_tlast is asserted number of output streaming data is NUMBER_OF_OUTPUT_WORDS-1          
//  // (0 to NUMBER_OF_OUTPUT_WORDS-1)                                                             
//  assign axis_tlast = (read_pointer == NUMBER_OF_OUTPUT_WORDS-1);                                
                                                                                                   
                                                                                                   
//  // Delay the axis_tvalid and axis_tlast signal by one clock cycle                              
//  // to match the latency of M_AXIS_TDATA                                                        
//  always @(posedge M_AXIS_ACLK)                                                                  
//  begin                                                                                          
//    if (!M_AXIS_ARESETN)                                                                         
//      begin                                                                                      
//        axis_tvalid_delay <= 1'b0;                                                               
//        axis_tlast_delay <= 1'b0;                                                                
//      end                                                                                        
//    else                                                                                         
//      begin                                                                                      
//        axis_tvalid_delay <= axis_tvalid;                                                        
//        axis_tlast_delay <= axis_tlast;                                                          
//      end                                                                                        
//  end                                                                                            


//  //read_pointer pointer

//  always@(posedge M_AXIS_ACLK)                                               
//  begin                                                                            
//    if(!M_AXIS_ARESETN)                                                            
//      begin                                                                        
//        read_pointer <= 0;                                                         
//        tx_done <= 1'b0;                                                           
//      end                                                                          
//    else                                                                           
//      if (read_pointer <= NUMBER_OF_OUTPUT_WORDS-1)                                
//        begin                                                                      
//          if (tx_en)                                                               
//            // read pointer is incremented after every read from the FIFO          
//            // when FIFO read signal is enabled.                                   
//            begin                                                                  
//              read_pointer <= read_pointer + 1;                                    
//              tx_done <= 1'b0;                                                     
//            end                                                                    
//        end                                                                        
//      else if (read_pointer == NUMBER_OF_OUTPUT_WORDS)                             
//        begin                                                                      
//          // tx_done is asserted when NUMBER_OF_OUTPUT_WORDS numbers of streaming data
//          // has been out.                                                         
//          tx_done <= 1'b1;                                                         
//        end                                                                        
//  end                                                                              


//  //FIFO read enable generation 

//  assign tx_en = M_AXIS_TREADY && axis_tvalid;   
                                                         
//      // Streaming output data is read from FIFO       
//      always @( posedge M_AXIS_ACLK )                  
//      begin                                            
//        if(!M_AXIS_ARESETN)                            
//          begin                                        
//            stream_data_out <= 1;                      
//          end                                          
//        else if (tx_en)// && M_AXIS_TKEEP[byte_index]  
//          begin                                        
//            stream_data_out <= read_pointer + 32'b1;   
//          end                                          
//      end                                              

    // Add user logic here

    ///////////////////////////
    // Naive implementation
    ///////////////////////////
    
//    assign M_AXIS_TVALID   = par_en && int_valid;
//    assign M_AXIS_TDATA    = {3'b0, int_valid, int_sop, int_eop, int_mod, int_data};
//    assign M_AXIS_TLAST    = int_eop;
//    assign M_AXIS_TKEEP    = {(C_M_AXIS_TDATA_WIDTH/8){1'b1}};
  
    /////////////////////////////////////////////
    // (PART I)
    // Store-Forward Buffering implementation
    /////////////////////////////////////////////

    /////////////////////////////////////////////
    // (CODE BLOCK 1) DC FIFO INSTANTIATION
    /////////////////////////////////////////////
    
    // FIFO_DUALCLOCK_MACRO: Dual Clock First-In, First-Out (FIFO) RAM Buffer
    //                       Artix-7
    // Xilinx HDL Language Template, version 2017.1
    
    /////////////////////////////////////////////////////////////////
    // DATA_WIDTH | FIFO_SIZE | FIFO Depth | RDCOUNT/WRCOUNT Width //
    // ===========|===========|============|=======================//
    //   37-72    |  "36Kb"   |     512    |         9-bit         //
    //   19-36    |  "36Kb"   |    1024    |        10-bit         //
    //   19-36    |  "18Kb"   |     512    |         9-bit         //
    //   10-18    |  "36Kb"   |    2048    |        11-bit         //
    //   10-18    |  "18Kb"   |    1024    |        10-bit         //
    //    5-9     |  "36Kb"   |    4096    |        12-bit         //
    //    5-9     |  "18Kb"   |    2048    |        11-bit         //
    //    1-4     |  "36Kb"   |    8192    |        13-bit         //
    //    1-4     |  "18Kb"   |    4096    |        12-bit         //
    /////////////////////////////////////////////////////////////////
    
    wire                            DATA_FIFO_RST;
    wire                            DATA_FIFO_WRCLK;
    wire                            DATA_FIFO_WREN;
    wire [C_M_AXIS_TDATA_WIDTH-1:0] DATA_FIFO_DI;
    wire                            DATA_FIFO_FULL;
    wire                            DATA_FIFO_RDCLK;
    wire                            DATA_FIFO_RDEN;
    wire [C_M_AXIS_TDATA_WIDTH-1:0] DATA_FIFO_DO;
    wire                            DATA_FIFO_EMPTY;
    FIFO_DUALCLOCK_MACRO  #(
       .ALMOST_EMPTY_OFFSET(9'h080), // Sets the almost empty threshold
       .ALMOST_FULL_OFFSET(9'h080),  // Sets almost full threshold
       .DATA_WIDTH(C_M_AXIS_TDATA_WIDTH),   // Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
       .DEVICE("7SERIES"),  // Target device: "7SERIES" 
       .FIFO_SIZE ("36Kb"), // Target BRAM: "18Kb" or "36Kb" 
       .FIRST_WORD_FALL_THROUGH ("FALSE") // Sets the FIFO FWFT to "TRUE" or "FALSE" 
    ) DATA_FIFO (
       .RST  (DATA_FIFO_RST),               // 1-bit input reset
       .WRCLK(DATA_FIFO_WRCLK),             // 1-bit input write clock
       .WREN (DATA_FIFO_WREN),              // 1-bit input write enable
       .DI   (DATA_FIFO_DI),                // Input data, width defined by DATA_WIDTH parameter
       .FULL (DATA_FIFO_FULL),              // 1-bit output full
       .RDCLK(DATA_FIFO_RDCLK),             // 1-bit input read clock
       .RDEN (DATA_FIFO_RDEN),              // 1-bit input read enable
       .DO   (DATA_FIFO_DO),                // Output data, width defined by DATA_WIDTH parameter
       .EMPTY(DATA_FIFO_EMPTY),             // 1-bit output empty
       .ALMOSTEMPTY(           ), // 1-bit output almost empty
       .ALMOSTFULL(          ),   // 1-bit output almost full
       .RDCOUNT(       ),         // Output read count, width determined by FIFO depth
       .RDERR(     ),             // 1-bit output read error
       .WRCOUNT(       ),         // Output write count, width determined by FIFO depth
       .WRERR(      )             // 1-bit output write error
    );

    wire          CTRL_FIFO_RST;
    wire          CTRL_FIFO_WRCLK;
    wire          CTRL_FIFO_WREN;
    wire [16-1:0] CTRL_FIFO_DI;
    wire          CTRL_FIFO_FULL;
    wire          CTRL_FIFO_RDCLK;
    wire          CTRL_FIFO_RDEN;
    wire [16-1:0] CTRL_FIFO_DO;
    wire          CTRL_FIFO_EMPTY;
    FIFO_DUALCLOCK_MACRO  #(
       .ALMOST_EMPTY_OFFSET(9'h080), // Sets the almost empty threshold
       .ALMOST_FULL_OFFSET(9'h080),  // Sets almost full threshold
       .DATA_WIDTH(16),   // Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
       .DEVICE("7SERIES"),  // Target device: "7SERIES" 
       .FIFO_SIZE ("18Kb"), // Target BRAM: "18Kb" or "36Kb" 
       .FIRST_WORD_FALL_THROUGH ("FALSE") // Sets the FIFO FWFT to "TRUE" or "FALSE" 
    ) CTRL_FIFO (
       .RST  (CTRL_FIFO_RST),               // 1-bit input reset
       .WRCLK(CTRL_FIFO_WRCLK),             // 1-bit input write clock
       .WREN (CTRL_FIFO_WREN),              // 1-bit input write enable
       .DI   (CTRL_FIFO_DI),                // Input data, width defined by DATA_WIDTH parameter
       .FULL (CTRL_FIFO_FULL),              // 1-bit output full
       .RDCLK(CTRL_FIFO_RDCLK),             // 1-bit input read clock
       .RDEN (CTRL_FIFO_RDEN),              // 1-bit input read enable
       .DO   (CTRL_FIFO_DO),                // Output data, width defined by DATA_WIDTH parameter
       .EMPTY(CTRL_FIFO_EMPTY),             // 1-bit output empty
       .ALMOSTEMPTY(           ), // 1-bit output almost empty
       .ALMOSTFULL(          ),   // 1-bit output almost full
       .RDCOUNT(       ),         // Output read count, width determined by FIFO depth
       .RDERR(     ),             // 1-bit output read error
       .WRCOUNT(       ),         // Output write count, width determined by FIFO depth
       .WRERR(      )             // 1-bit output write error
    );
    
    /////////////////////////////////////////
    // (CODE BLOCK 2) WRITE FIFO LOGIC
    /////////////////////////////////////////
    
    // write DFIFO
    // GENERAL MAPPING
    wire                            dfifo_wren = par_en && int_valid;
    wire [C_M_AXIS_TDATA_WIDTH-1:0] dfifo_din  = int_data;
    
    // write CFIFO
    reg          int_eop_d1 = 1'b0;
    always @(posedge int_clk) if (par_en) int_eop_d1 <= int_valid && int_eop;
    reg          cfifo_din_pbad;
    always @(posedge int_clk or posedge int_rst) begin
        if (int_rst)
            cfifo_din_pbad <= 1'b0;
        else if (par_en)
            if      (int_valid && DATA_FIFO_FULL)
                cfifo_din_pbad <= 1'b1;  // set
            else if (int_eop_d1)
                cfifo_din_pbad <= 1'b0;  // clear
    end
    reg  [14-1:0] cfifo_din_pcnt;
    always @(posedge int_clk or posedge int_rst) begin
        if (int_rst)
            cfifo_din_pcnt <= 14'd0;
        else if (par_en)
            if (int_valid && int_sop)
                cfifo_din_pcnt <= 14'd4;  // init
            else if (int_valid && int_eop)
                cfifo_din_pcnt <= cfifo_din_pcnt + ((int_mod==2'd0)? 14'd4: {12'd0, int_mod});  // last
            else if (int_valid)  // incr
                cfifo_din_pcnt <= cfifo_din_pcnt + 14'd4;
    end
    reg          cfifo_wren_reg;
    always @(posedge int_clk or posedge int_rst) begin
        if (int_rst)
            cfifo_wren_reg <= 1'b0;
        else if (par_en)
            cfifo_wren_reg <= int_valid && int_eop;
    end
    // GENERAL MAPPING
    wire          cfifo_wren = par_en && cfifo_wren_reg;
    wire [16-1:0] cfifo_din  = {cfifo_din_pbad, 1'd0, cfifo_din_pcnt};  // {1,1,14}
    
    /////////////////////////////////////////
    // (CODE BLOCK 3) READ FIFO LOGIC
    /////////////////////////////////////////
    
    // fsm input signals
    wire          dfifo_read_done;
    // fsm output signals
    reg  cfifo_rden_reg;
    reg  dfifo_rden_reg;
   // GENERAL MAPPING
   wire dfifo_rden = dfifo_rden_reg && M_AXIS_TREADY && !DATA_FIFO_EMPTY;
   wire cfifo_rden = cfifo_rden_reg;
    
    // fsm state transition
    reg  [ 7:0] fsm_read_curr_st, fsm_read_next_st, fsm_read_last_st;
    
    parameter [ 7:0]
    FSM_READ_IDLE    =                       0,  // 0
    FSM_READ_CTRL    = FSM_READ_IDLE       + 1,  // 1
    FSM_READ_DATA    = FSM_READ_CTRL       + 1;  // 2
    
    always @(negedge M_AXIS_ARESETN or posedge M_AXIS_ACLK) begin
        if (!M_AXIS_ARESETN) begin
            fsm_read_curr_st <= FSM_READ_IDLE;
            fsm_read_last_st <= FSM_READ_IDLE;
        end
        else if (1'b1) begin
            fsm_read_curr_st <= fsm_read_next_st;
            fsm_read_last_st <= fsm_read_curr_st;
        end
    end
    
    always @(*) begin
        case (fsm_read_curr_st)
            FSM_READ_IDLE:
                if (!CTRL_FIFO_EMPTY)
                    fsm_read_next_st = FSM_READ_CTRL;
                else
                    fsm_read_next_st = FSM_READ_IDLE;
            FSM_READ_CTRL:
                    fsm_read_next_st = FSM_READ_DATA;
            FSM_READ_DATA:
                if (dfifo_read_done)
                    fsm_read_next_st = FSM_READ_IDLE;
                else
                    fsm_read_next_st = FSM_READ_DATA;
            default:
                fsm_read_next_st = FSM_READ_IDLE;
        endcase
    end
    
    // fsm input logic
    wire [13:0] packet_leng = CTRL_FIFO_DO[13:0];
    wire        packet_drop = CTRL_FIFO_DO[15];
    reg  [16-1:0] dfifo_read_rcnt;
    always @(negedge M_AXIS_ARESETN or posedge M_AXIS_ACLK) begin
        if (!M_AXIS_ARESETN)
            dfifo_read_rcnt <= 14'd0;
        else if (fsm_read_next_st == FSM_READ_IDLE)
            dfifo_read_rcnt <= 14'd0;
        else if (dfifo_rden)
            dfifo_read_rcnt <= dfifo_read_rcnt + 14'd4;
    end
    assign dfifo_read_done = (dfifo_read_rcnt+14'd4 >= packet_leng)? 1'b1:1'b0;    
    
    // fsm output logic
    always @(negedge M_AXIS_ARESETN or posedge M_AXIS_ACLK) begin
        if (!M_AXIS_ARESETN)
            {cfifo_rden_reg, dfifo_rden_reg} <= {1'b0, 1'b0};
        else begin
            if (fsm_read_next_st == FSM_READ_CTRL)
                cfifo_rden_reg <= 1'b1;
            else
                cfifo_rden_reg <= 1'b0;
                
            if (fsm_read_next_st == FSM_READ_DATA)
                dfifo_rden_reg <= 1'b1;
            else
                dfifo_rden_reg <= 1'b0;
        end
    end
    
    /////////////////////////////////////////
    // (CODE BLOCK 4) FIFO SIGNAL MAPPING
    /////////////////////////////////////////
    
    assign DATA_FIFO_RST   = !M_AXIS_ARESETN;
    assign DATA_FIFO_WRCLK = int_clk;
    assign DATA_FIFO_WREN  = dfifo_wren && !DATA_FIFO_FULL;
    assign DATA_FIFO_DI    = dfifo_din;
    //assign DATA_FIFO_FULL  = ;
    assign DATA_FIFO_RDCLK = M_AXIS_ACLK;
    assign DATA_FIFO_RDEN  = dfifo_rden && !DATA_FIFO_EMPTY;
    //assign DATA_FIFO_DO    = ;
    //assign DATA_FIFO_EMPTY = ;
    
    assign CTRL_FIFO_RST   = !M_AXIS_ARESETN;
    assign CTRL_FIFO_WRCLK = int_clk;
    assign CTRL_FIFO_WREN  = cfifo_wren && !CTRL_FIFO_FULL;
    assign CTRL_FIFO_DI    = cfifo_din;
    //assign CTRL_FIFO_FULL  = ;
    assign CTRL_FIFO_RDCLK = M_AXIS_ACLK;
    assign CTRL_FIFO_RDEN  = cfifo_rden && !CTRL_FIFO_EMPTY;
    //assign CTRL_FIFO_DO    = ;
    //assign CTRL_FIFO_EMPTY = ;
        
    /////////////////////////////////////////
    // (PART II)
    // AXI-S MASTER SIGNAL GENERATION
    /////////////////////////////////////////
    
    /////////////////////////////////////////
    // (CODE BLOCK 1) AXI-S MASTER SIGNAL GENERATION
    /////////////////////////////////////////
    
    reg                                 axis_tvalid;
    wire [    C_M_AXIS_TDATA_WIDTH-1:0] axis_tdata  = DATA_FIFO_DO;
    reg                                 axis_tlast;
    reg  [(C_M_AXIS_TDATA_WIDTH/8)-1:0] axis_tstrb;
    always @(negedge M_AXIS_ARESETN or posedge M_AXIS_ACLK) begin
        if (!M_AXIS_ARESETN)
            axis_tvalid <= 1'b0;
        else
            axis_tvalid <= dfifo_rden && !packet_drop;
    end
    always @(negedge M_AXIS_ARESETN or posedge M_AXIS_ACLK) begin
        if (!M_AXIS_ARESETN)
            axis_tlast <= 1'b0;
        else
            axis_tlast <= (fsm_read_curr_st == FSM_READ_DATA) && dfifo_read_done;
    end
    always @(posedge M_AXIS_ACLK) begin
        if (!dfifo_read_done)
            axis_tstrb = {(C_M_AXIS_TDATA_WIDTH/8){1'b1}};
        else
            case (packet_leng[1:0])
                2'b00: axis_tstrb = 4'b1111;
                2'b01: axis_tstrb = 4'b0001;
                2'b10: axis_tstrb = 4'b0011;
                2'b11: axis_tstrb = 4'b0111;
            endcase
    end
    
    /////////////////////////////////////////
    // (CODE BLOCK 2) AXI-S MASTER SIGNAL MAPPING
    /////////////////////////////////////////
    
    assign M_AXIS_TVALID   = axis_tvalid;
    assign M_AXIS_TDATA    = axis_tdata;
    assign M_AXIS_TLAST    = axis_tlast;
    assign M_AXIS_TKEEP    = axis_tstrb;
    
    // User logic ends

    endmodule
